1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, by which leakage current is reduced by minimizing electron or hole density in a source/drain forming a P/N junction with a channel area of a transistor.
2. Discussion of the Related Art
Generally, as a semiconductor size is reduced according to a highly increasing degree of semiconductor device integration, a channel length of a semiconductor device is reduced as well. The characteristics of the semiconductor device can be balanced only if the dimensional reduction of the semiconductor is horizontally and vertically made. If such a requirement for the dimensional reduction of the semiconductor device fails to be met, a channel length between source and drain is shortened to result in unfavorable variations of the semiconductor device characteristics such as the short channel effect (SCE).
To overcome the short channel effect, a horizontal reduction in a gate electrode width and the like needs to be simultaneously made together with a vertical reduction in gate insulating layer thickness, source/drain junction depth, and the like. Moreover, according to the horizontal and vertical reductions, a voltage of a power source is lowered, a doping density of a semiconductor substrate is raised, and more specifically, a doping profile in a channel area should be efficiently controlled.
Yet, since the operational power requested by an electronic product is still high despite the dimensional reduction of the semiconductor device, electrons injected from a source of an NMOS transistor are severely accelerated in a potential gradient state of a drain to make the NMOS transistor vulnerable to hot carrier generation for example. To overcome such a problem, an LDD (lightly doped drain) structure improving the NMOS transistor vulnerable to hot carriers has been proposed.
In a transistor of the LDD structure, a lightly doped region (n−) lies between a channel and a heavily doped drain/source (n+) to buffer a high drain voltage in the vicinity of the drain junction. Hence, the lightly doped region interrupts the abrupt potential variation to suppress the hot carrier generation. Since many efforts have been made to development of a highly increased degree of semiconductor device integration, various methods for fabrication LDD MOSFET have been proposed. One of the various methods is an LDD fabrication method using a spacer provided to a sidewall of a gate electrode, which is currently and mostly adopted as a method for mass production.
A method of fabricating a semiconductor device having an LDD structure according to a related art is explained as follows.
FIG. 1A and FIG. 1B are cross-sectional diagrams for explaining a method of fabricating a semiconductor device having an LDD structure according to a related art.
Referring to FIG. 1A, a device isolation layer 102 is formed on a field area of a semiconductor substrate 101 to define an active area of the semiconductor substrate 201 such as a P type silicon substrate 101.
Channel ions for threshold voltage adjustment of a channel area are implanted into a surface of the semiconductor substrate 101 to form a channel ion region 104.
A gate oxide layer 103, e.g., an oxide layer 103, is grown on the active area of the semiconductor substrate 101 by thermal oxidation.
A polysilicon layer is deposited on the gate insulating layer 103 and is then patterned by photolithography to form a pattern of a gate electrode 105.
Subsequently, LDD ion implantation is carried out on the substrate 101 to form a pair of lightly doped regions 106 for an LDD structure aligned with the pattern of the gate electrode 105.
Referring to FIG. 1B, a sidewall insulating layer 106, e.g., a TEOS oxide layer, is deposited over the substrate 101 including the gate electrode 105 and the active area.
And, an insulating layer 107, e.g., a nitride layer 107, for a spacer is deposited on the sidewall insulating layer 106.
The insulating layer 107 is etched back to form a spacer 108 on a sidewall of the gate electrode 105.
Subsequently, source/drain ion implantation is carried out on the substrate 101, whereby a pair of heavily doped regions in the active area of the substrate 201 to be aligned with the spacer 108. Hence, self-aligned N type source S and drain D are formed in the active area of the substrate 101.
Thereafter, the sidewall insulating layer 106 is removed by wet etch to expose a topside of the gate electrode 105 and surfaces of the source S and drain D.
However, in the transistor fabricated by the related art method, the channel ion region and the source/drain region configure a P/N junction which becomes in a reverse bias state on operating the transistor. And, a depletion area having no electron or hole exists in the P/N junction area. Moreover, it is highly probable that leakage current is generated from the depletion area by an electric field.
Meanwhile, amplitude of the electric field is proportional to density of electrons or holes. In order to minimize the leakage current occurrence in the depletion area, the electric field of the corresponding area needs to be lowered. And, the density of electrons or holes should be lowered to reduce the electric field.